Field of the Invention
The present invention relates generally to a semiconductor device. More specifically, the invention relates to electrostatic breakdown or damage protection for a semiconductor integrated circuit on a semiconductor substrate.
A technique for providing electrostatic breakdown protection for a semiconductor integrated circuit has been disclosed in Japanese Unexamined Patent Publication (Kokai) No. Heisei 7-86510.
FIG. 1 is a circuit diagram showing one example of such a conventional semiconductor device. As shown in FIG. 1, the conventional semiconductor device is provided with a plurality of voltage clamping (VC) elements 2A to 2M and a plurality of diode elements 3A to 3M connected to respective terminals in parallel as protection elements. A common discharge line 18 is provided for discharging an electrostatic pulse applied to respective terminals namely, a power source (VCC) terminal 10, an input terminal 11, Gnd terminal 12, an output circuit power source (VCCQ) terminal 13, an output terminal 14, an output circuit GndQ terminal 15, an internal circuit Gnd terminal 16 and other terminal 17 and so forth, of the semiconductor integrated circuit constructed with an internal circuit 4, an inverter 5 connected to the internal circuit 4, an output transistor 6, a protection resistor 7 and a BVDS transistor 8. The common discharge line 18 has a wiring structure constructed in common with a SUB wiring connected to a back-bias generator (BBG circuit) 9 which is connected to substrate 21 (see FIG. 2) for supplying a potential to the semiconductor substrate 21 to maintain a constant substrate voltage therein, in order to avoid increasing chip area.
In case of a dynamic memory (DRAM) a negative potential is applied to the semiconductor substrate. As a potential supply method, aluminum wiring is provided at the outermost circumference (scribe line region) of the semiconductor substrate for connection with the substrate to provide a negative potential to the substrate as substrate potential by means of the BBG circuit 9. Therefore, the substrate per se assumes a floating condition to an external terminal.
As set forth above, in the conventional semiconductor device, the SUB wiring is employed as the common discharge line 18 for protection from electrostatic breakdown.
FIG. 2 is a section of a scribe line region on the semiconductor substrate including the circuit for FIG. 1. As shown in FIG. 2, the conventional semiconductor device includes in the scribe line region 25 formed at the outermost circumference of the chip, a field oxide layer 22 on a P-type substrate (P-Sub) 21, a P-type diffusion layer 23 therebetween, and an interlayer insulation layer 24 and the common discharge line 18 on the diffusion layer 23. In such device, the substrate 21 is connected to terminals 10-17 via voltage clamping elements 2A-2M and diode elements 3A-3M. As a result, the substrate 21 is isolated from these terminals except for a time when an electrostatic pulse is applied to at least one of terminals 10-17.
FIG. 3 is a plan view showing layout on the chip including the circuit shown in FIG. 1. As shown in FIG. 3, the chip 30 is formed by arranging on substrate 21 an internal circuit 4 at the center portion and the common discharge line 18 in a loop at the outermost circumference (scribe line region). In order to protect the internal circuit 4, the common discharge line 18 is connected to the input terminal 11 via a protection element, to the Gnd terminal 16 via a protection element, and to the BBG circuit 9. Furthermore, the common discharge line 18 is connected to the semiconductor substrate 21 through diffusion region 23 as shown in FIG. 2.
Each of terminals 10 to 17 of the conventional semiconductor device as set forth above, are connected to the common discharge line 18 by the voltage clamping elements 2A to 2M and the diode elements 3A to 3M in parallel connection. In conjunction therewith, the BBG circuit 9 maintaining a substrate voltage constant also connects its output transistor to the common discharge line 18.
For example, in the circuit of FIG. 1, the Gnd terminal 16 becomes a discharging terminal and the voltage clamping element 2B is turned ON, when a positive electrostatic pulse is applied to the input terminal 11. A voltage where the clamping element 2B should be turned ON is set to be higher than an absolute maximum rating of the power source voltage VCC and to be lower than a withstanding voltage of the gate oxide layer and PN junction. It should be noted that between the input terminal 11 and the gate of an inverter circuit 5, a protection resistor 7 is provided so that the peak of the electrostatic pulse may not directly influence the inverter circuit 5.
Accordingly, after turning ON the clamping element 2B, an electrostatic pulse applied to the input terminal 11 is discharged to GND terminal 16 via voltage clamping element 2G and the common discharge line 18.
The conventional semiconductor device prevents electrostatic breakdown with respect to the internal circuit 4 by providing a discharge path as set forth above.
The above-mentioned conventional semiconductor device integrates the common discharge line and the SUB wiring as an electrostatic breakdown protection device. Accordingly, if the semiconductor substrate is at ground level, the discharge pulse is discharged to the ground acting as a discharging terminal via the common discharge line without passing through the clamping element and the diode so as not to cause the problem of electrostatic breakdown.
However, in some semiconductor devices, such as a DRAM, a negative potential is frequently applied to the semiconductor substrate. In such cases, it becomes necessary to provide the BBG circuit as the circuit for applying the negative potential to the semiconductor substrate on the discharge path of the electrostatic pulse. Therefore, by connecting the output transistor of the BBG circuit to the common discharge line, the following problems are encountered.
Namely, the first problem is that when the electrostatic pulse is applied to the input terminal 11 the Gnd terminal 16 becomes a discharging terminal in FIG. 3, and the electrostatic pulse applied to the input terminal 11 is discharged to the Gnd terminal 16 via the common discharge line 18. However, the gate and drain of the output transistor of the BBG circuit 9 are also connected to the common discharge line 18. Thus, when the electrostatic pulse is repeatedly applied, it is possible to cause breakdown of a PN junction of the output transistor of the BBG circuit.
A reason for the breakdown in the junction is the flowing of a large current. For example, in an electrostatic breakdown test by the C-V charge method, when a pulse of discharge voltage .+-.2000V is charged, with a current at capacity of 100 pF and a resistance value of 1500.OMEGA., a large current of 1.33A flows at the peak.
However, a resistance value of the common discharge line 18 is increased as the loop distance increases due to greater chip side length. For example, for a chip 7 mm square, when the electrostatic pulse is applied to a terminal located at the most distanced position from the BBG circuit 9, the resistance value can be several tens of ohms. In fact, when the resistance value of the common discharge line 18 is assumed to be 20.OMEGA., 26.66V can be applied to the diffusion layer of the BBG circuit 9 and the gate oxide layer. When the withstanding voltage of the PN junction of the gate oxide layer is assumed to be several tens of volts, the voltage in excess of the withstanding voltage can be applied.
Therefore, when the common discharge line 18 and the SUB wiring are provided as a common wiring such as shown in FIG. 2, a transistor connected to the SUB circuit can breakdown. On the other hand, in consideration of the problem of breakdown, when a resistance value of the common discharge line 18 is to be limited to several ohms, the only measure to be taken is to increase the wiring width of the common discharge line 18. However, this increases chip size.
A second problem is that when the negative potential is applied to the substrate, the diffusion layer can be a source of electron injection to possibly cause breakdown in an N-type diffusion layer or the gate oxide layer of the Gnd and VCC terminals via the gate in the vicinity thereof. Such a problem has been known in recent years as GCD (Gate Controlled Diode) mode.
When an additional circuit is directly connected to the common discharge line, namely when a gate or diffusion layer of a transistor in the additional circuit is connected to the common discharge line, the additional circuit per se may breakdown.